Siemens SIMATIC IPC427C Operations Instructions Page 148

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Detailed descriptions
16.4 I/O Address Areas
SIMATIC IPC427C
148 Operating Instructions, 10/2010, A5E02414743-03
16.4.6 Battery status tab (read-only, address 50Fh)
The status of the CMOS battery is monitored; the status (two-tier) can be read from the
battery status register.
Meaning of the bits
Battery status register (read-only, address 50Fh)
Bit Description
7 6 5 4 3 2 1 0
0 0 CMOS battery capacity is still sufficient.
1 0 CMOS battery capacity is exhausted (remaining capacity is
sufficient for approx. one month)
1 1 CMOS battery is empty
16.4.7 SRAM address register
The battery-buffered SRAM uses a 2 MB memory address area, which can be read via the
PCI register.
Meaning of the bits
SRAM address register
PCI register address:
SRAM base address register
PCI register content:
SRAM memory address (default)
Length of the memory area
8010 2010h 9040 0000h
Address is assigned dynamically
(depending on device)
20 0000h
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