S7-300 Automation System CPU Specifications: CPU 31xC and CPU 31x
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3.1 Operator control and display elements .............................................................3-1
3.1.1 CPU 31xC: Operator control and display elements ..........................................3-1
3.1.2 CPU 31x: Operator control and display elements.............................................3-5
3.2 SIMATIC Micro Memory Card (MMC) ...............................................................3-9
3.3 Interfaces.........................................................................................................3-11
3.4 DPV1 functions................................................................................................3-14
3.5 Real-time clock................................................................................................3-16
3.6 S7 Connections ...............................................................................................3-17
3.7 Communications..............................................................................................3-21
3.8 Routing ............................................................................................................3-25
3.9 Data consistency .............................................................................................3-28
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4.1 Memory areas....................................................................................................4-1
4.1.1 Distribution of the memory ................................................................................4-1
4.1.2 Retentive memory .............................................................................................4-2
4.2 Memory functions ..............................................................................................4-5
4.3 Address areas ...................................................................................................4-8
4.4 Handling of DB data ........................................................................................4-11
4.4.1 Recipes............................................................................................................4-11
4.4.2 Measurement value archives ..........................................................................4-13
4.5 Saving/retrieving complete projects to/from Micro Memory Card ...................4-15
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5.1 Overview............................................................................................................5-1
5.2 Cycle Time.........................................................................................................5-2
5.2.1 Overview............................................................................................................5-2
5.2.2 Calculating the cycle time..................................................................................5-4
5.2.3 Different cycle times ..........................................................................................5-7
5.2.4 Communication load..........................................................................................5-9
5.2.5 Cycle time extension as a result of testing and commissioning functions ......5-11
5.3 Response Time ...............................................................................................5-12
5.3.1 Overview..........................................................................................................5-12
5.3.2 Shortest response time ...................................................................................5-14
5.3.3 Longest response time ....................................................................................5-15
5.3.4 Reducing the response time with direct I/O access ........................................5-16
5.4 Calculating method for calculating the cycle/response time ...........................5-17
5.5 Interrupt response time ...................................................................................5-18
5.5.1 Overview..........................................................................................................5-18
5.5.2 Reproducibility of delay interrupts and watchdog interrupts ...........................5-20
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