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TC65 Hardware Interface Description
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TC65_HD_V02.000 Page 34 of 120 08.06.2006
3.3.2 Signal States after Startup
Table 6 describes the various states each interface pin passes through after startup and
during operation.
As shown in
Figure 5 and Figure 6 the pins are in undefined state while the module is
initializing. Once the startup initialization has completed, i.e. when CTS is high and the
software is running, all pins are in defined state. The state of several pins will change again
once the respective interface is activated or configured by AT command.
Table 6: Signal states
Active state after configuration by AT command Signal name Undefined state
during startup
Defined state after
initialization
GPIO SPI I
2
C DAI
SYNC
O, L O, L
CCIN
I, PU(100k) I, PU(100k)
CCRST
O, L O, L
CCIO
O, L O, L
CCCLK
O, L O, L
CCVCC
O, L 2.9V
RXD0
I, PU O, H
TXD0 I, PU I, PD(330k)
CTS0 O, L O, L
RTS0 I, PU I, PD(330k)
DTR0 I, PU I
DCD0 O, L O, H
DSR0 O, L O, H
RING0 I, PU O, H
RXD1
O, H O, H
TXD1
I, PD(330k) I, PD(330k)
CTS1
L O, L
RTS1
I, PD(330k) I, PD(330k)
SPIDI
I Tristate I Tristate
SPICS
I O, H O, L Tristate
I2CDAT_SPIDO
I Tristate O, L/H IO
I2CCLK_SPICLK
I Tristate O, L/H O, OD
GPIO1 I, PU Tristate IO
GPIO2 I, PU Tristate IO
GPIO3 I, PU Tristate IO
GPIO4 I, PD Tristate IO
GPIO5 O, L Tristate IO
GPIO6 I Tristate IO
GPIO7 I Tristate IO
GPIO8 O, L Tristate IO
GPIO9 I Tristate IO
GPIO10 I Tristate IO
DAC_OUT O, L O, L
DAI0
I Tristate O, L
DAI1
I Tristate I
DAI2
I Tristate O, L
DAI3
I Tristate O, L
DAI4
I Tristate I
DAI5
I Tristate I
DAI6
I Tristate I
For abbreviations, see below.
- Hardware Interface Descri 1
- Contents 3
- Figures 6
- 0 Document History 7
- 1 Introduction 10
- 1.2 Terms and Abbreviations 11
- 1.3 Type Approval 14
- 1.4 Safety Precautions 16
- 2 Product Concept 18
- 2.2 TC65 System Overview 21
- 2.3 Circuit Concept 22
- 3 Application Interface 23
- 3.1 Operating Modes 24
- 3.2 Power Supply 26
- 3.3.1 Turn on TC65 28
- 31
- Table 6: Signal states 34
- 3.3.3 Turn off TC65 36
- 3.3.4 Automatic Shutdown 39
- 3.3.4.5 Overvoltage Shutdown 41
- 3.5 Charging Control 43
- 3.5.1 Hardware Requirements 43
- 3.5.2 Software Requirements 43
- 3.5.4 Charger Requirements 45
- 3.6 Power Saving 48
- AT interface disabled 49
- AT interface enabled 49
- 3.8 RTC Backup 51
- 3.9 SIM Interface 52
- 3.10 Serial Interface ASC0 53
- 3.11 Serial Interface ASC1 55
- 3.12 USB Interface 56
- C Interface 59
- Figure 20: I 60
- 3.14 SPI Interface 61
- SPI MODE 0 SPI MODE 1 62
- SPI MODE 2 SPI MODE 3 62
- Clock phase 62
- Clock polarity 62
- 3.15 Audio Interfaces 63
- 3.15.1 Speech Processing 64
- 3.15.2 Microphone Circuit 64
- GSM module 68
- Figure 29: PCM timing 70
- 3.17 GPIO Interface 72
- 3.18 Control Signals 73
- 3.18.4 PWR_IND Signal 75
- 4 Antenna Interface 76
- Antenna 77
- 4.2 Antenna Pad 78
- 4.2.1 Suitable Cable Types 78
- 4.3 Antenna Connector 79
- 5.2 Operating Temperatures 84
- 5.3 Storage Conditions 85
- EMRG_RST 89
- 5.6 Power Supply Ratings 95
- 5.7.4 Voiceband Receive Path 101
- 5.8 Air Interface 103
- 5.9 Electrostatic Discharge 104
- 6 Mechanics 105
- Confidential / Released 106
- 7 Sample Application 111
- 8 Reference Approval 113
- 9 Appendix 115
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