Bit Logic Instructions
Statement List (STL) for S7-300 and S7-400 Programming
A5E00706960-01
1-21
1.21 CLR Clear RLO (=0)
Format
CLR
Description
CLR sets the RLO to signal state "0".
Status word
BR CC 1 CC 0 OV OS OR STA RLO /FC
writes: - - - - - 0 0 0 0
Example
Statement List Signal State Result of Logic Operation (RLO)
SET
= M 10.0
= M 15.1
= M 16.0
CLR
= M 10.1
= M 10.2
1
0
1
1
1
0
0
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